The patent applications MEMORY HAVING MULTIPLE WRITE PORTS AND MULTIPLE CONTROL MEMORY UNITS, AND METHOD OF OPERATION, Carter, Ser. No. 10/326,779 and MEMORY HAVING MULTIPLE WRITE PORTS AND WRITE INSERT UNIT, AND METHOD OF OPERATION, Carter, Ser. No. 10/326,405, are filed concurrently with the present application and incorporated herein by reference.
1. Field of the Invention
The present invention relates generally to memory devices, and more particularly, to providing a more capable memory from less capable memory components.
2. Background Information
It is known to combine multiple memory components, such as static random access memory devices, to produce a larger memory array having enhanced capability. For example, smaller memory components can be combined in an array to form a wider memory (i.e., a memory wherein the addressable locations include a larger number of bits). Each of the smaller memory components that form the array have common address and control signals, but have separate data in and data out signals. Alternately, smaller memory components can be combined into an array to form a larger memory of increased depth (i.e., a memory with a large number of addressable locations). Such arrays involve the use of decoders and read data multiplexers. In combining smaller memory components to form a memory array, focus has been on the desired width or depth of the memory array, and the address signals used.
Some design systems allow designers to create a circuit of connected components selected from a design library. The maximum number of write ports on any memory device to be included in the circuit is limited by the memory components available in the design library. For the case of Field Programmable Gate Arrays (FPGAs), the design library includes the primitive hardware structures of the FPGA (e.g. configurable logic blocks or block RAMs) and any higher-level design elements provided by a xe2x80x9ccore generatorxe2x80x9d or other such FPGA design tools. Similarly, for Application Specific Integrated Circuits (ASICs), the design library includes a fixed number of standard-cell or other pre-verified component designs. For these and other technologies, any design that involves a memory with more than the maximum number of write ports supported by the design library is unrealizable in that technology.
Exemplary embodiments of the present invention are directed to providing a memory having N write ports, where N is greater than one. The memory includes a first data memory unit having a plurality of storage locations addressable by a range of addresses and having less than N write ports; the memory also includes a second data memory unit having a plurality of storage locations addressable by the range of addresses, the second data memory having less than N write ports. The memory further includes a control unit configured to select among the first and second memory units in response to a read command having an associated read address which falls within the address range. The control unit includes multiple control memory units each with less than N write ports.
Exemplary embodiments of the present invention are also directed to a method for operating a memory including the steps of providing a memory having N write ports, where N is greater than one. The memory is constructed from multiple data memory units each having less than N write ports and a range of addressable storage locations, and a control unit including multiple control memory units, each with less than N write ports. The method comprises supplying information to an addressable location of the memory which falls within the range of addressable locations, and updating the at least one control memory unit in the control unit so that the data in the control memory unit for the addressable storage location can be used to determine the data memory unit that contains the most recently written data for the addressable location.
Exemplary embodiments of the present invention are further directed to a system including a memory. The memory has N write ports, wherein N is greater than 1. The memory includes a first data memory unit having a plurality of storage locations addressable by a range of addresses. The first data memory unit has less than N write ports. The memory includes a second data memory unit having a plurality of storage locations addressable by the range of addresses. The second data memory unit has less than N write ports. The memory includes a control unit configured to select among the first data memory unit and the second data memory unit in response to a read command having an associated read address which falls within the address range. The control unit includes multiple control memory units each with less than N write ports. The system includes logic configured to access the memory.